FIG. 5 shows an arrangement of a conventional active matrix substrate 905 having a multi-pixel structure (i.e., active matrix substrate 905 of a pixel division method).
As illustrated in FIG. 5, the active matrix substrate 905 has data signal lines 915 extending in a column direction Y, scanning signal lines 916 extending in a line direction X, retention capacitor lines 918 extending in the line direction X, and pixel regions 903 defined by the data signal lines 915 and the scanning signal lines 916.
Each of the retention capacitor lines 918 centrally crosses corresponding pixel regions 903. In each of the pixel regions 903, a transistor 912 and a pixel electrode 917 are formed.
Specifically, in each of the pixel regions 903, a source electrode 908 of the transistor 912 is connected with a corresponding data signal line 915, and a drain electrode 909 of the transistor 912 is connected with a corresponding pixel electrode 917 via a contact hole 911.
A corresponding scanning signal line 916 serves as a gate electrode of the transistor 912.
As mentioned earlier, each of the retention capacitor lines 918 and a corresponding pixel electrode 917 overlap each other. As a result, a retention capacitor is formed between each of the retention capacitor lines 918 and a corresponding pixel electrode 917.
In a liquid crystal display apparatus having the active matrix substrate 905, a part corresponding to each of the pixel regions 903 is one pixel. In the liquid crystal display apparatus, a signal potential is supplied from each of the data signal lines 915 to a corresponding pixel electrode 917.
In the active matrix substrate 905 illustrated in FIG. 5, spare lines are provided so that a defect such as a break of a data signal line 915 may be corrected. The following describes this.
In the active matrix substrate 905, retention capacitor line extensions 918s are provided so as to extend from an intersection RC1 of a corresponding retention capacitor line 918 and a corresponding data signal line 915 toward each of intersections RC2 and RC3, which are adjacent to the intersection RC1, of the data signal line 915 and two scanning signal lines 916.
Specifically, the two retention capacitor line extensions 918s are provided so as to extend, along the data signal line 915, from the intersection RC1 lying substantially on a halfway line of corresponding pixel regions 903, while leaving gaps on both sides of the data signal line 915 in planar view.
In addition, the two retention capacitor line extensions 918s are extended right before each of the intersections RC2 and RC3.
In other words, no retention capacitor line extension 918s intersects with any scanning signal line 916, and, in planer view, a constant gap is formed between a tip of each retention capacitor line extension 918s and a corresponding scanning signal line 916. This is because, in general, the retention capacitor lines 918, the retention capacitor line extensions 918s, and the scanning signal lines 916 are formed at a same layer level.
Any two retention capacitor line extensions 918s which are provided along a corresponding data signal line 915 and on both sides thereof each have retention capacitor line extension projections 918sc which project toward the data signal line 915.
Each of the two retention capacitor line extension projections 918sc overlaps the data signal line 915 in planar view (See overlapping points P1, P2, P3, and P4 in FIG. 5).
Specifically, any two retention capacitor line extensions 918s sandwiching a corresponding data signal line 915 each have two retention capacitor line extension projections 918sc between corresponding intersections RC1 and RC2. That is, the two retention capacitor line extensions 918s have four retention capacitor line extension projections 918sc in total between the intersections RC1 and RC2.
Similarly, four retention capacitor line extension projections 918sc are also provided between corresponding intersections RC1 and RC3.
Two retention capacitor line extension projections 918sc are provided to one of two retention capacitor line extensions 918s which face each other across a corresponding data signal line 915 while the other two retention capacitor line extension projections 918sc are provided at substantially same positions of the other one of the two retention capacitor line extensions 918s. In other words, in a region where the data signal line 915 and two retention capacitor line extension projections 918sc which face each other across the data signal line 915 overlap each other, the two retention capacitor line extension projections 918sc overlap the data signal line 915 from both sides thereof.
In the active matrix substrate 905 illustrated in FIG. 5, the overlapping points formed between the intersections RC1 and RC2 are intersections P1 and P2 which lie in this order from the intersection RC1. On the other hand, the overlapping points formed between the intersections RC1 and RC3 are intersections P3 and P4 which lie in this order from the intersection RC1.
As described above, in the conventional active matrix substrate 905 illustrated in FIG. 5, each of the retention capacitor line extensions 918s is provided along a corresponding data signal line 915. Further, each of the retention capacitor line extensions 918s (retention capacitor line extension projections 918sc) and a corresponding data signal line 915 are provided so as to overlap each other.
Therefore, in a case where a data signal line 915 has a defect such as a break, the defect can be recovered (corrected) by using, as a bypass, a corresponding retention capacitor line extension 918s provided along the data signal line 915. That is, the retention capacitor line extension 918s is used as a so-called spare line so that a signal potential may be transmitted via the spare line. This makes it possible to supply the data signal to a part behind the break.
Patent Literature 1 can be taken as one of publicly-known documents related to the conventional active matrix substrate.
Citation List
Patent Literature 1
Japanese Patent Application Publication, Tokukaihei, No. 11-38449 A (Publication Date: Feb. 12, 1999)